Data driver circuit for a plasma display device

ABSTRACT

In a data driver circuit for a plasma display device having a first data electrode and a second electrode that are disposed adjacently each other, the data driver circuit having: a first circuit means for outputting first display data to the first data electrode; a second circuit means for outputting second display data to the second data electrode; and an output timing control means for controlling a timing of outputting the first display data from the first circuit means to the first data electrode or a timing of outputting the second display data from the second circuit means to the second data electrode.

SPECIFICATION

[0001] A data driver circuit for a plasma display device

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a drive circuit of a plasmadisplay device, and more particularly to a data driver having a functionthat reduces noise attributed to display data, generated at the time ofelectrode voltage switching.

[0004] 2. Related Art

[0005] In a plasma display of the surface discharge type, row and columnelectrodes are provided on two glass substrates, respectively, adielectric layer being provided above the row electrodes of the rowelectrode glass substrate and a phosphor layer being provided over thecolumn electrodes of the column electrode glass substrate havingpartition walls, a discharge space being provided between two substratesfacing each other and a gas being sealed between the above-mentioned twosubstrates, which form display panel having a planar matrix structure,in which the row electrodes and the column electrodes are independentlydriven, so as to cause a plasma discharge at the intersection (cell)between driven row and column electrodes, thereby exiting the phosphorlayer provided on the column electrodes so that it emits light. In thecase of a display panel that produces a color display, each columnelectrode is made up of electrodes for three colors having phosphorlayer for red (R), green (G), and blue (B), each of the color electrodesfor each column being driven separately so as to produce a color displayhaving a plurality of colors.

[0006] Additionally, as the row electrodes, X electrodes and electrodesare provided. The X electrodes provided in common for each row and the Yelectrodes provided for each row are alternately disposed. In theabove-noted case, when driving these electrodes, a voltage pulse isapplied alternating between the X and Y electrodes, thereby causing adischarge that reverses the electrode each half cycle. This type ofdriving method is known as AC drive method.

[0007] In an AC plasma display panel (AC-PDP) as described above, once adischarge occurs between the electrodes of each cell, the electrons andions generated in the discharge space are accumulated on the phosphorlayer, thereby forming a wall charge, after the formation of which it ispossible because of the action of the wall charge to cause a dischargewith a low voltage, and it is possible to sustain the discharge byalternating this low voltage each half cycle. This function is called asa memory function, the discharge sustained by the low voltage based onthe memory function is called as sustaining charge.

[0008] In an AC-PDP, in order to achieve a gradation representation, thevideo signal during a single field period is divided into a plurality ofsub-fields, the time (number of times) during which a discharge issustained for each sub-field being controlled. More specifically, foreach sub-field, after resetting, by assigning a sustaining dischargeperiod that increases in proportion to 2^(n), for example, the greateris the number of sustaining discharges made, the brighter will be thelight from a cell, thereby performing a gradation representation.

[0009] The configurations of an AC-PDP and a conventional data drivercircuit and the operation thereof are described below.

[0010]FIG. 9 of the accompanying drawings, is a block diagram showingthe configuration of an AC color PDP to which the prior art and thepresent invention could be applied, FIG. 10 is a drawing showing theconfiguration of a data driver circuit of the past, FIG. 11 is a timingdiagram showing the format of the display data input to the data drivercircuit, and FIG. 12 is a flowchart illustrating the output operation ofthe data driver circuit.

[0011] As shown in FIG. 9, an AC-PDP 100 has a plurality of data drivercircuits 101A, 101B, 101C, . . . , 101E, an AC type plasma display panel(AC-PDP) 102, scan driver circuits 103A, . . . , 103C, a formatconversion circuit 104, a drive signal generating circuit 105, and ahigh-voltage drive circuit 106.

[0012] The data driver circuits 101A, 101B, 101C, . . . , 101E, whichare formed by integrated circuits, receive from the format conversioncircuit 104 a prescribed number (n) of serial display data signals at atime corresponding to the N column electrodes, and output data inparallel to the column electrodes for each scan period in response to aparallel latch control signal from the drive signal generating circuit105.

[0013] The AC-PDP 102 is an AC-driven type plasma display panel, whichperforms drive in accordance with a sub-field sequence using a memoryfunction, and has a matrix electrode arrangement having M rows of rowelectrodes and N columns of column electrodes (data electrodes)corresponding to the three colors R, G, and B for each of the columns.The scan driver circuits 103A, . . . , 103C, which are formed byintegrated circuits, in response to row drive signals from the drivesignal generating circuit 105 for each prescribed number of rows,sequentially output scan signals to the M rows of row electrodes.

[0014] The format conversion circuit 104 converts the format of videodata having the three colors R, B, and G by using frame memories 111,and the converted three colors R, G, and B signals are sequentiallyarranged for each column, and the serial display data signals are outputfrom the format conversion circuit 104.

[0015] The drive signal generating circuit 105, in response to avertical synchronization signal included in the video data signaldetected by a vertical synchronization signal detection circuit (notshown in the drawing), according to a prescribed sequence for eachfield, generates row and column drive signals, and supplies thesesignals to the data driver circuits 101A, 101B, 101C, . . . , 103E, andto the scan driver circuits 103A, . . . , 103C. The high-voltage drivecircuit 106, in response to a drive signal from the drive signalgenerating circuit 105, supplies a high-voltage to each of the datadriver circuits 101A, 101B, 101C, . . . , 101E.

[0016] A data driver circuit 101 of the past, as shown in FIG. 10,generally comprises an n-stage shift register circuit 11, a parallellatch circuit 12 with n circuits, n output control logic gates G1, G2,G3, G4, . . . , Gn, and n high withstand voltage CMOS (complementarymetal oxide semiconductor) drivers B1, B2, B3, B4, . . . , Bn. In theAC-PDP 102 as shown in FIG. 10, the electrode structure for each of thethree colors R, G, and B in each column is abbreviated to just a singledata electrode DL that is shown.

[0017] The shift register circuit 11 is formed by an n-stage shiftregister, and acts to shift the serial display data signal DS input fromthe frame memory 111 for each scan period at a time. The parallel latchcircuit 12 latches the outputs from the n-stage shift register of theshift register circuit 11 in response to a parallel latch control signalΦ from the drive signal generating circuit 105.

[0018] The output control gate circuits G1, G2, G3, G4, . . . , Gn, inresponse to an output control signal OS from the drive signal generatingcircuit 105, output signals Q1, Q2, Q3, Q4, . . . , Qn from the parallellatch circuit 12 for each scan period. The high-voltage CMOS drivers B1,B2, B3, B4, . . . , Bn, by using the high-voltage supply Vd from thehigh-voltage drive circuit 106, convert the parallel signals Q1, Q2, Q3,Q4, . . . , Qn from the output control gate circuits G1, G2, G3, G4, . .. , Gn to data signals O1, O2, O3, O4, . . . , On, which arehigh-voltage write pulses, these being output to the data electrodes ofthe AC-PDP 102.

[0019] The output states of the data driver circuit 111, as shown inFIG. 11, have two forms. In FIG. 11, FIG. 11(a) shows the case of 1-bitdata output, and FIG. 11(b) shows the case of 3-bit data output.

[0020] In the case of 1-bit data output, as shown in FIG. 11(a), theinput data DS are repeatedly arranged in the sequence of R, G, and B,the shift register circuit 11 shifts these data DS at each rising edgeof the shift clock, and when the final shift is reached, at the fallingedge, for example, of the parallel latch control signal the data arelatched into the parallel latch circuit 12, output being made therefromone bit at a time, for example as the serial display data signalsequence On, On-1, On-2, On-3, On-4, On-5, On-6, . . . , O3, O2, O1.

[0021] In the case of 3-bit data output, as shown in FIG. 11(b),although input data DS are same data as FIG. 11(a), R, G, and B inputdata are grouped by 3 bits at a time in the sequence of R, G, and B,then the shift register circuit 11 shifts R, G, and B at a rising edgeof the shift clock signal SC. When the shift register circuit 11 shiftsthe last input data, the shifted data by the shift register circuit 11is latched by the parallel latch circuit 12 at the falling edge of theparallel latch control signal Φ. The serial display data signal 1, theserial display data signal 2, and the serial display data 3 are groupedinto one group, and output by 3 bits at a time in the sequence (On,On-1, On-2), (On-3, On-4, On-5), (On-6, On-7, On-8) . . . , (O3, O2,O1).

[0022] The operation of an AC-PDP device of the past is described below,with references to FIG. 9 through FIG. 12.

[0023] An AC-PDP has a configuration such as shown in FIG. 9, in which avideo data signal serially input to the format conversion circuit 104for each of the colors R, G, and B is divided in accordance with numberof data outputs from the data driver circuit 101, and converted data aretransferred serially to each data driver circuit 101A, 101B, 101C, . . ., 101E during the scan period by using separate signal lines.

[0024] At each of the data driver circuits, the serial display datasignal DS for each color that was transferred in serial fashion, inresponse to the shift clock signal SC, is arranged in an R, G, and Bsequence and input to the shift register circuit 11, the output from theshift register circuit 11 being latched by the parallel latch circuit 12in accordance with the parallel latch control signal Φ. Parallel outputsignals are generated in the output control logic gate circuits G1, G2,G3, G4, . . . , Gn, in response to the output control signal OS. Theseparallel output signals are input to the high-voltage CMOS driver B1,B2, B3, 4, . . . , Bn at the same time so as to generate thehigh-voltage write pulse data signals O1, O2, O3, O4, . . . , On, thenthese high-voltage write pulse data signals are output to each of thedata electrodes of the AC-PDP 102.

[0025] In this case, at each of the data driver circuits, as shown inFIG. 12, in response to the rising edge of the output control signal OS,by inputting the parallel input signal Q to the high-voltage CMOS driverB via the output control logic gate circuit G, conversion is made of thehigh level of the parallel input signal Q to the high power supplyvoltage Vd, and conversion is made of the low level to 0 V for output,so that, in response to the parallel input signal Q, the high powersupply voltage Vd is applied to the data electrode, thereby causing adischarge at a cell at an intersection with a row electrode that isbeing scanned.

[0026] In a AC-PDP of the past, when data is written to the dataelectrodes during sub-fields from the data driver circuit, between agiven sub-field and a sub-field therebefore or thereafter if the datachanges from the condition in which all the data signals are “on” stateto the condition in which all the data signals are “off” state, or ifthe levels of all the data signals change in the reverse direction fromthe above, there is the problem of noise occurring at the dataelectrodes of the AC-PDP when switching occurs of the high-voltage ofthe data signals.

[0027]FIG. 13 is a timing diagram illustrating the noise occurring in adata driver circuit of the past and FIG. 14 is a timing diagramillustrating noise occurring in a data driver circuit of the past.

[0028]FIG. 13 shows the case in which adjacent outputs are switched tobe the same potential, in which case when the parallel input signals Q1,Q2, and Q3 corresponding to the three adjacent data electrodes drive thehigh-voltage CMOS drivers G1, G2, and G3, so as to drive thehigh-voltage CMOS drivers B1, B2, and B3, the high power supply voltageVd being switched so as to convert it to the data signals O1, O2, and O,the voltages at each of the data electrode are relatively the same, andbecause it is not possible to achieve a discharge load by means of theinter-electrode capacitances C1 and C2 between adjacent electrodes, asudden change in voltage occurs, thereby causing the large switchingnoise indicated by the arrows at the rising edge and falling edge ofeach of the data signals.

[0029] In FIG. 14, which shows the case in which there is switching ofadjacent outputs that are mutually differing potential at the same time,similar to the case shown in FIG. 13, the parallel input signals Q1, Q2,and Q3 corresponding to three adjacent data electrodes cause switchingof the high-voltage supply voltage Vd at the respective high withstandvoltage CMOS drivers B1, B2, and B3, so as to convert it to the datasignals O1, O2, and O, the voltages at each of the data electrodes beingrelatively increased, resulting in switching noise at the rising edgeand falling edge of each data signal being suppressed. In this case,because it is possible to achieve a discharge load by means of theinter-electrode capacitances C1 and C2 between adjacent electrodes.

[0030] In an AC-PDP, depending upon the spatial and temporal arrangementof the display data, there are cases in which the changes that will be asame potential at the same time on adjacent data electrodes occur, inwhich case, as shown in FIG. 13, charging and discharging of theelectrostatic charge between the electrodes do not occur, so that thereis a sudden rise in the voltage waveform and the switching currents ofthe adjacent data electrodes flow in the same direction, resulting in alarge amount of noise occurring.

[0031] This noise causes a change in the ground level, and this noisebecomes an interference noise to the display data. Such interference canmanifest itself as dot or line noise on the display screen that is notexistent in the original video signal, or noise propagating on the powerline increases, or an EMI (electromagnetic interference) increases.

[0032] Accordingly, the present invention was made in consideration ofthe above-noted situation, and has as an object to provide a data drivercircuit which, in an AC-PDP or the like, by reducing the opportunity fora change that becomes the same potential at the same time on adjacentdata electrodes to occur, achieves a charging/discharging load betweenadjacent data electrodes at the time of switching of high-voltage dataon a data electrode based on a change in the display data, therebysuppressing a sudden change in the switching voltage waveform andreducing the occurrence of noise.

SUMMARY OF THE INVENTION

[0033] To achieve the above-noted object, the present invention has thefollowing basic technical constitution.

[0034] The first aspect of the present invention is a data drivercircuit for a plasma display device having a first data electrode and asecond electrode that are disposed adjacently to each other, the datadriver circuit comprising: a first circuit means for outputting firstdisplay data to the first data electrode; a second circuit means foroutputting second display data to the second data electrode; and anoutput timing control means for controlling a timing of outputting thefirst display data from the first circuit means to the first dataelectrode or a timing of outputting the second display data from thesecond circuit means to the second data electrode.

[0035] The second aspect of the present invention is a data drivercircuit for a plasma display device having a first data electrode and asecond electrode that are disposed adjacently to each other, the datadriver circuit comprising: a first latch circuit for latching firstdisplay data for outputting to the first data electrode; a second latchcircuit for latching second display data for outputting to the seconddata electrode; a first latch signal for the first latch circuit; asecond latch signal for the second latch circuit; and a latch timingcontrol means for controlling a latch timing of the first display databy the first latch signal or a latch timing of the second display databy the second latch signal; wherein the latch timing of the second latchcircuit is different from that of the first latch circuit.

[0036] In the third aspect of the present invention, the data drivercircuit further comprising: a time difference generating means forcontrolling the latch timing control means in accordance with the firstdisplay data and the second display data; wherein the time differencegenerating means generates a time difference between the latch timing ofthe first latch circuit and the latch timing of the second latchcircuit.

[0037] The fourth aspect of the present invention is a data drivercircuit for a plasma display device having a first data electrode and asecond electrode that are disposed adjacently to each other, the datadriver circuit comprising: a first circuit means for outputting firstdisplay data to the first data electrode at a first timing; a secondcircuit means for outputting second display data to the second dataelectrode at the first timing or a second timing that is different fromthe first timing; and an output timing control means for selectingeither the first timing or the second timing so as to control an outputtiming of the second circuit means.

[0038] The fifth aspect of the present invention is a data drivercircuit for a plasma display device having a first data electrode and asecond electrode that are disposed adjacently to each other, the datadriver circuit comprising: a first latch circuit for latching firstdisplay data for outputting to the first data electrode; a second latchcircuit for latching second display data for outputting to the seconddata electrode; a latch signal for the second latch circuit; and a latchtiming control means for controlling a latch timing of the seconddisplay data by the latch signal; wherein the latch timing of the secondlatch circuit is different from that of the first latch circuit.

[0039] The sixth aspect of the present invention is a data drivercircuit for a plasma display device having a first data electrode and asecond electrode that are disposed adjacently to each other, the datadriver circuit comprising: a first latch circuit for latching firstdisplay data for outputting to the first data electrode; a second latchcircuit for latching second display data for outputting to the seconddata electrode; a first latch signal for the first latch circuit; and asecond latch signal, a latch timing of which being different from thatof the first latch circuit, for the second latch circuit.

[0040] The seventh aspect of the present invention is a data drivercircuit for a plasma display device having a first data electrode and asecond electrode that are disposed adjacently to each other, the datadriver circuit comprising: a first circuit means for outputting firstdisplay data to the first data electrode; a second circuit means foroutputting second display data to the second data electrode; and a delaymeans provided in the second circuit means so as to delay an outputtiming of the second display data with respect to that of the firstdisplay data.

BRIEF DESCRIPTIONS OF THE DRAWINGS

[0041]FIG. 1 is a drawing showing the configuration of a data drivercircuit according to a first embodiment of the present invention.

[0042]FIG. 2 is a timing diagram illustrating the generation ofswitching noise in the first embodiment of the present invention.

[0043]FIG. 3 is another timing diagram illustrating the generation ofswitching noise in the first embodiment of the present invention.

[0044]FIG. 4 is a drawing showing the configuration of a data drivercircuit according to a second embodiment of the present invention.

[0045]FIG. 5 is a drawing showing the configuration of a data drivercircuit according to a third embodiment of the present invention.

[0046]FIG. 6 is a block diagram showing the configuration of data leveldifference signal generator circuit and time difference generatorcircuit shown in FIG. 5.

[0047]FIG. 7 is a timing diagram illustrating the operation of the datalevel difference generator circuit and timing difference generatorcircuit.

[0048]FIG. 8 is a drawing showing the configuration of a data drivercircuit according to a fourth embodiment of the present invention.

[0049]FIG. 9 is a block diagram showing the configuration of a colorAC-PDP device to which the prior art and the present invention areapplied.

[0050]FIG. 10 is a drawing showing the configuration of a conventionaldata driver circuit.

[0051]FIG. 11 is a timing diagram showing the display data input formatof the data driver circuit.

[0052]FIG. 12 is a timing diagram illustrating the output operation of adata driver circuit.

[0053]FIG. 13 is a timing diagram illustrating the generation ofswitching noise in the conventional data driver circuit.

[0054]FIG. 14 is another timing diagram illustrating the generation ofswitching noise in the conventional data driver circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0055] Embodiments of the present invention are described in detailbelow, with reference made to relevant accompanying drawings.

[0056] (First embodiment)

[0057]FIG. 1 is a drawing showing the configuration of a data drivercircuit according to a first embodiment of the present invention, FIGS.2 and 3 are timing diagrams illustrating the generation of noise in thefirst embodiment of the present invention.

[0058] The data driver circuit 1 of the present invention, as shown inFIG. 1, is generally formed by an n-stage shift register circuit 11, nparallel latch circuits 12, n output control logic gate circuits G1, G2,G3, G4, . . . , and Gn, n latch circuits L1, L2, L3, L4, . . . , and Lnformed by D-type flip-flops or the like, and n high withstand voltageCMOS drivers B1, B2, B3, B4, . . . , and Bn.

[0059] Of the above-noted elements, because the shift register circuit11, the parallel latch circuits 12, the output control logic gatecircuits G1, G2, G3, G4, . . . , and Gn, and the high withstand voltageCMOS drivers B1, B2, B3, B4, . . . , Bn are similar to the case of theprior art, shown in FIG. 9, they will not be described in detail herein.

[0060] Of the latch circuits L1, L2, L3, L4, . . . , and Ln, theodd-numbered latch circuits L1, L3, and so on, latch output signals fromthe respective odd-numbered output control 3 logic gate circuits G1, G3,and so on, in response to an applied external latch control signal Φ1,these being input to the high withstand voltage CMOS drivers B1, B3, andso on, so that the high withstand voltage CMOS drivers B1, B3 and so onswitch the high supply voltage Vd and output the data signals O1, O3,and so on. Similarly, the even-numbered latch circuits L2, L4, and soon, latch output signals from the respective even-numbered outputcontrol logic gate circuits G2, G4, and so on, in response to an appliedexternal latch control signal Φ2, these being input to the highwithstand voltage CMOS drivers B2, B4, and so on, so that the highwithstand voltage CMOS drivers B2, B4 and so on switch the high supplyvoltage Vd and output the data signals O2, O4, and so on.

[0061] The operation of the data driver circuit of the first embodimentis described below, with references made to FIG. 1, FIG. 2, and FIG. 3.

[0062] A serial display data signal DS input to the data driver circuit1 from a format conversion circuit 104 is input to the shift registercircuit 11 for each scan period in response to a shift clock signal SCfrom the drive signal generating circuit 105, the output from the shiftregister circuit 11 being latched by the parallel latch circuits 12 inresponse to a parallel latch control signal Φ from the drive signalgenerating circuit 105. The output control logic gate circuits G1, G2,G3, G4, . . . , and Gn output the parallel input signals Q1, Q2, Q3, Q4,. . . , and Qn from the parallel latch circuits 12 in parallel inresponse to the output control signal OS from the drive signalgenerating circuit 105.

[0063] Of the latch circuits L1, L2, L3, L4, . . . , Ln, theodd-numbered latch circuits L1, L3 and so on, in response to anexternally applied latch control signal φ1 latch the respective outputsignals from the odd-numbered output control logic gate circuits G1, G3,and so on, and input them to the high withstand voltage CMOS drivers B1,B3, and so on so that the high withstand voltage CMOS drivers B1, B3,and so on switch the high power supply voltage Vd and output the datasignals O1, O3, and so on. Similarly, the even-numbered latch circuitsL2, L4 and so on, in response to an externally applied latch controlsignal φ2 latch the respective output signals from the even-numberedoutput control logic gate circuits G2, G4, and so on, and input them tothe high withstand voltage CMOS drivers B2, B4, and so on so that thehigh withstand voltage CMOS drivers B2, B4, and so on switch the highpower supply voltage Vd and output the data signals O2, O4, and so on.

[0064] When this occurs, a time difference τ is imparted between theexternally applied latch control signals φ1 and Φ2 in the case in whichan external circuit (not shown in the drawing) detects that a changethat becomes the same potential at the same time on the data signals onadjacent electrodes occurs frequently during one scan period.

[0065] The phase of the output signals of the output control logic gatecircuits G1, G2, G3, G4, . . . , and Gn, and those of parallel inputsignals Q1, Q2, Q3, Q4, . . . , and Qn, are same. However, the latchcontrol signals φ2 rises with respect to latch control signals φ1 in apredetermined time τ. That is, the latch control signals φ2 delays withrespect to latch control signals φ1. Therefore, the input signals ofeven-numbered high withstand voltage CMOS drivers B2, B4, . . . , delaywith respect to those of the odd-numbered high withstand voltage CMOSdrivers B1, B3, . . . , for a predetermined time τ, respectively.Accordingly, the even-numbered data signals O2, O4, . . . , delay withrespect to those of the odd-numbered data signals O1, O3, . . . , for apredetermined time τ.

[0066] As constituting the above, for example, during the even-numbereddata signals O2, O4, . . . , are outputting, the odd-numbered datasignals O1, O3, . . . , do not output, so that it is possible to achievea charging/discharging load by means of inter-electrode capacitances C1and C2 between adjacent data electrodes at the time of switching ofhigh-voltage data, thereby suppressing a sudden change in the switchingvoltage waveform and reducing the occurrence of noise.

[0067] In this case, even if achieving a charging/discharging load bymeans of inter-electrode capacitances, the time required for switchingin the high withstand voltage CMOS drivers is generally approximately 3nS to 14 ns, so that the time delay to be imparted to the latch controlsignal φ2 is only approximately 100 ns. Accordingly, it easy to impartthe delay time τ between the latch control signals φ1 and φ2.

[0068] In FIG. 2, the adjacent output signals Q1, Q2, Q3 simultaneouslychange to be the same potential. However, there is a time difference Tbetween the latch control signals Φ1 and φ2. Therefore, theeven-numbered data signal O2 delays τ with respect to the odd-numbereddata signals O1, O3. In this case, it is possible to achieve acharging/discharging load by means of inter-electrode capacitances C1and C2 between adjacent data electrodes at the time of switching ofhigh-voltage data, thereby suppressing a sudden change in the switchingvoltage waveform and reducing the occurrence of noise.

[0069] In FIG. 3, the adjacent output signals Q1, Q2, Q3 simultaneouslychange to be the different potential. However, there is a timedifference τ between the latch control signals Φ1 and φ2. Therefore, thepotentials of the odd-numbered data signals O1 and O3 and theeven-numbered data signal O2 change to be the different potential, andfurther there is a time difference τ therebetween, so that, it ispossible to achieve a charging/discharging load by means ofinter-electrode capacitances C1 and C2 between adjacent data electrodesat the time of switching of high-voltage data, thereby suppressing asudden change in the switching voltage waveform and reducing theoccurrence of noise.

[0070] In general, there are two methods for imparting of a timedifference between the odd-numbered data signals and the even-numbereddata signals, one method being a method for imparting a time differencefor all signals during one scan period, and the other method is a methodin which imparting a time difference is performed when potentials of allor a majority of the data signals output from the data driver circuitchange to be a same potential at the same time during one scan period.

[0071] Although the method in which a time difference is provided to alladjacent data electrodes during one scan period has the advantage ofbeing able to implement it without the need for a complex circuit,because the imparting of a time difference to data signals at adjacentdata electrodes applies restraints on the time required to establish thestability of the output to a data electrode, there is a danger that thethere will not be enough time to write a high-voltage data to a dataelectrode, thereby causing an abnormality in light output condition. Toprevent such problems, there are cases in which the operating speed ofthe AC-PDP itself be reduced.

[0072] Because the probability of noise being generated is great whenpotentials of data change to be the same potential with a highfrequency, by detecting the frequency at which potentials of data changeto be the same potential and imparting a time difference to the datasignals between adjacent data electrodes, it is possible to preventnoise without affecting the performance of the AC-PDP itself. However,this requires a circuit to detect the frequency of data voltageschanging to be the same potential, thereby making the configuration morecomplex.

[0073] Therefore, the externally applied latch control signals Φ1 and φ2are determined in accordance with the purpose and function of the AC-PDPdevice.

[0074] According to a data driver circuit configured as described inthis embodiment, because there is a time difference between odd-numberedhigh-voltage signals and even-numbered high-voltage signals inaccordance with externally applied latch control signals φ1 and φ2, evenif potentials of data changes to be the same potential at the same time,it is possible to achieve a charging/discharging load by means of theinter-electrode capacitance, thereby suppressing a sudden change in thevoltage waveform when high-voltage data is switched at data electrodes,and reducing the accompanying switching noise.

[0075] (Second embodiment)

[0076]FIG. 4 shows the configuration of a data driver circuit accordingto a second embodiment of the present invention.

[0077] As shown in FIG. 4, this data driver circuit 1A is generallyformed by an n-stage shift register circuit 11, n parallel latchcircuits 12, n output control logic gate circuits G1, G2, G3, G4, . . ., and Gn, n latch circuits L1, L2, L3, L4, . . . , and Ln, n highwithstand voltage CMOS drivers B1, B2, B3, B4, . . . , and Bn, and anall-white/all-black signal generating circuit/time difference generatingcircuit 13.

[0078] Of the above-noted elements, because the shift register circuit11, the parallel latch circuits 12, the output control logic gatecircuits G1, G2, G3, G4, . . . , and Gn, and the high withstand voltageCMOS drivers B1, B2, B3, B4, . . . , Bn are similar to the case of theprior art, shown in FIG. 9, they will not be described in detail herein.

[0079] In this embodiment, the configuration and function of the latchcircuits L1, L2, L3, L4, . . . , and Ln are similar to the firstembodiment illustrated in FIG. 1, with the difference being that latchcontrol signals φ1A and φ2A, rather than being applied from outside, areapplied from an all-white/all-black signal generating circuit/timedifference generating circuit 13 provided within the data driver circuit1A.

[0080] The all-white/all-black signal generating circuit/time differencegenerating circuit 13 is formed by an all-white/all-black signalgenerating circuit and a time difference generating circuit. Theall-white/all-black signal generating circuit, by taking the logical ANDof all the data output in parallel from the parallel latch circuit 12,detects a condition in which all the data of the data driver circuit areoutput and generates an all-white detection signal, and by taking thelogical NOR of all the data output in parallel from the parallel latchcircuit 12, detects the condition in which no data signal is beingoutput, and generates an all-black detection signal, and by making acomparison between the logical AND of the previous scan period and thecurrent scan period and the logical NOR of the previous scan period andthe current scan period, generates an all-white/all-black detectionsignal if an all-white signals and an all-black signals are detectedcontinuously.

[0081] The latch control signal φ1A is output to the odd-numbered latchcircuits L1, L3 and so on, and the latch control signal φ2A is output tothe even-numbered latch circuits L2, L4, and so on. When this is done ifthe all-white/all-black detection signal is not generated, the latchcontrol signals φ1A and φ2A are generated with the same timing, but ifthe all-white/all-black detection signal is generated, a prescribed timedifference is imparted between the latch control signals φ1A and φ2A, sothat the latch control signal Φ2A is delayed by a prescribed time τrelative to the latch control signal φ1A.

[0082] The operation of the data driver circuit of this embodiment isthe same as indicated for the first embodiment shown in FIG. 1, with theexception of the generation of the latch control signals φ1A and φ2Awithin the all-white/all-black signal generating circuit/time differencegenerating circuit 13 provided in the data driver circuit.

[0083] In this case, in the time difference generating circuit, asdescribed in the first embodiment, because the time delay to be impartedto the latch control signal φ2A is only approximately 100 ns, it ispossible to achieve this delay time using the gate delay of the requirednumber of series-connected inverters or the like, making it easy toimpart the delay time τ between the latch control signals φ1A and φ2A.

[0084] In this manner, by adopting a configuration in which a timedifference is provided between the even-numbered high-voltage datasignals and the odd-numbered high-voltage data signals output from thedata driver circuit in accordance with the latch control signals φ1A andφ2A output from the all-white/all-black signal generating circuit/timedifference generating circuit 13 provided within the data drivercircuit, it is possible to achieve a charging/discharging load by meansof the capacitance between adjacent data electrodes, in response to thedetection of a condition in which potentials on adjacent data electrodeschange to be the same potential at the same time, thereby suppressing asudden change in the voltage when the high-voltage data voltage isswitched at the data electrodes, and reducing the accompanying switchingnoise that is generated.

[0085] (Third embodiment)

[0086]FIG. 5 is a drawing showing the configuration of a data drivercircuit according to a third embodiment of the present invention, FIG. 6is a drawing showing an example of the configuration of data leveldifference signal generator circuit and time difference generatorcircuit, and FIG. 7 is a timing diagram illustrating the operation ofthe data level difference generator circuit and timing differencegenerator circuit.

[0087] As shown in FIG. 5, this data driver circuit 1B is generallyformed by an n-stage shift register circuit 11, n parallel latchcircuits 12, n output control logic gate circuits G1, G2, G3, G4, . . ., and Gn, n latch circuits L1, L2, L3, L4, . . . , and Ln, n highwithstand voltage CMOS drivers B1, B2, B3, B4, . . . , and Bn, and adata level difference signal generating circuit/time differencegenerating circuit 14.

[0088] Of the above-noted elements, because the shift register circuit11, the parallel latch circuits 12, the output control logic gatecircuits G1, G2, G3, G4, . . . , and Gn, and the high withstand voltageCMOS drivers B1, B2, B3, B4, . . . , Bn are similar to the case of theprior art, shown in FIG. 9, they will not be described in detail herein.

[0089] In this embodiment, the configuration and function of the latchcircuits L1, L2, L3, L4, . . . , and Ln are similar to the firstembodiment illustrated in FIG. 1, with the difference being that latchcontrol signals φ1B and φ2B, rather than being applied from outside, areapplied from a data level difference signal generating circuit/timedifference generating circuit 14 provided within the data driver circuit1B.

[0090] The data level difference signal generating circuit/timedifference generating circuit 14 is formed by a data level differencegenerating circuit and a time difference generating circuit. In the datalevel difference signal generating circuit, when the number ofhigh-level data among all the data output in parallel from the parallellatch circuit 12 is greater than a first threshold value Th1, the datalevel signal generating circuit outputs a white priority signal, andwhen the number of data thereamong is below a second threshold value Th2(where Th1>Th2), the data level signal generating circuit outputs ablack priority signal, a comparison being made of the white prioritysignal and the black priority signal for the previous scan period andcurrent scan period in response to the parallel latch control signal Φ,and if the black priority signal and white priority signal are detectedcontinuously, the data level difference signal is output.

[0091] The time difference generating circuit outputs a latch controlsignal Φ1B for the odd-numbered latch circuits L1, L3, and so on, andoutputs a latch control signal φ2B for the even-numbered latch circuitsL2, L4, and so on, and when this is done, when the data level differencesignal is not generated the latch control signals φ1B and φ2B are outputat the same timing. However, if the level difference signal isgenerated, a prescribed time difference is imparted between the latchcontrol signals φ1B and φ2B, so that the latch control signal φ2B isdelayed by a prescribed time T relative to the latch control signal φ1B.

[0092] In this embodiment, the data level difference signal generatingcircuit/time difference generating circuit 14 is formed, as shown inFIG. 6, by a counter 21, a level detection circuit 22, a thresholdsetting circuit 23, D-type flip-flops 24 and 25, a data level differencedetection circuit 26, and a time difference generating circuit 27.

[0093] The counter 21 counts the high-level data in the serial displaydata signal DS at the rising edge of the shift clock signal SC. Thecounter 21 is reset by the parallel latch control signal Φ. The leveldetection circuit 22 compares the count value of the counter 21 with thefirst threshold value Th1 and the second threshold value Th2 set by thethreshold value setting circuit 23, and generates a white priority orblack priority signal in accordance comparison results.

[0094] The D-type flip-flops 24 and 25, in response to the parallellatch control signal Φ, shift and store the white priority signal dataor black priority signal data output from the level detection circuit22. If the data level difference detection circuit 26 detects continuouswhite priority signals or black priority signals at the output of theD-type flip-flops 24 and 25, the data level difference detection circuit26 outputs a data level difference signal. In response to the data leveldifference signal output from the data level difference signal detectioncircuit 26, the time difference generating circuit 27 generates thelatch control signals φ1B and φ2B with the above-noted time difference τtherebetween.

[0095] The operation of counting the number of the high-level data inthe data level difference signal generating circuit/time differencegenerating circuit 14 is described below, with reference made to FIG. 7.

[0096] The counter 21, as it is reset by the parallel latch controlsignal Φ, counts up the number of high-level serial display data signalsDS for one scan period, at the rising edge of the shift clock SC, so asto generate a count value CT.

[0097] The operation of the data driver circuit of this embodiment isthe same as that of the first embodiment, with the exception of thegeneration of the latch control signals φ1B and φ2B within the datalevel difference signal generating circuit/time difference generatingcircuit 14 of the data driver circuit.

[0098] In this case, because the method of imparting the time differenceτ to the latch control signals φ1B and φ2B in the time differencegenerating circuit is the same as described for the second embodiment,it will not be described in detail herein.

[0099] In this manner, by adopting a configuration in which a timedifference is provided between the even-numbered high-voltage datasignals and the odd-numbered high-voltage data signals output from thedata driver circuit in accordance with the latch control signals φ1B andφ2B output from the data level difference signal generating circuit/timedifference generating circuit 14 provided within the data drivercircuit, it is possible to achieve a charging/discharging load by meansof the capacitance between adjacent data electrodes, in response to thedetection of a condition in which potentials on adjacent data electrodeschange to be the same potential at the same time, thereby suppressing asudden change in the voltage when the high-voltage data voltage isswitched at the data electrodes, and reducing the accompanying switchingnoise that is generated.

[0100] In the case of this embodiment, the frequency at which potentialschange to be the same potential at the same time on adjacent electrodesis detected by comparing threshold values and a charging/dischargingload is achieved, so that, compared with the second embodiment, it ispossible to increase the opportunities to suppress a sudden change inthe voltage waveform at the time of switching of the high voltage atdata electrodes.

[0101] (Fourth embodiment)

[0102]FIG. 8 shows the configuration of a data driver circuit accordingto a fourth embodiment of the present invention.

[0103] As shown in FIG. 8, this data driver circuit 1C is formed by ann-stage shift register circuit 11, n parallel latch circuits 12, noutput control logic gate circuits G1, G2, G3, G4, . . . , and Gn, nhigh withstand voltage CMOS drivers B1, B2, B3, B4, . . . , and Bn andalternately skipped delay elements DL1, DL3, and so on disposed betweenodd-numbered output control logic gate circuits G1, G3, and so on, andcorresponding odd-numbered high withstand voltage CMOS drivers B1, B3,and so on.

[0104] Of the above-noted elements, because the shift register circuit11, the parallel latch circuits 12, the output control logic gatecircuits G1, G2, G3, G4, . . . , and Gn, and the high withstand voltageCMOS drivers B1, B2, B3, B4, . . . , Bn are similar to the case of theprior art, shown in FIG. 9, they will not be described in detail herein.

[0105] The delay elements DL1, DL3, and so on in this embodiment cause adelay of a prescribed time τ in the output signal from the outputcontrol logic gate circuits G1, G3, and so on relative to the outputsfrom the output control logic gate circuits G2, G4, and so on.

[0106] In the data driver circuit of this embodiment, by providing thedelay elements DL1, DL3, and so on, the data output signals O1, O3, andso on from the odd-numbered high-voltage CMOS drivers B1, B3, and so onare delayed by a prescribed time τ relative to the output signals O2,O4, and so on from the even-numbered high-voltage CMOS drivers B2, B4,and so on.

[0107] Therefore, even if the data signal voltages are relatively thesame, because there is a time difference of τ between the odd-numbereddata signals O1, O3, and so on and the even-numbered data signals O2,O4, and so on, in the case in which, during the even-numbered datasignals O2, O4, . . . , are outputting, the odd-numbered data signalsO1, O3, . . . , do not output, so that it is possible to achieve acharging/discharging load by means of inter-electrode capacitances C1and C2 between adjacent data electrodes at the time of switching ofhigh-voltage data, thereby suppressing a sudden change in the switchingvoltage waveform and reducing the occurrence of noise.

[0108] In this case, because the delay time τ in which the data signalsO1, O3, and so on from the odd-numbered high withstand CMOS drivers B1,B3 and so on delay by virtue of the delay elements DL1, DL3, and so on,is only approximately 100 ns, as described in the first embodiment, itis possible to achieve this delay time using the gate delay of therequired number of series-connected inverters or the like.

[0109] In this manner, by adopting a data driver circuit having aconfiguration in which a time difference is provided between theeven-numbered high-voltage data signals and the odd-numberedhigh-voltage data signals by using delay elements DL1, DL3, and so on,regardless of whether or not there the change in voltage at adjacentdata electrodes, it is possible to achieve a charging/discharging loadby means of the capacitance between adjacent data electrodes, therebyenabling suppression of a sudden change in voltage waveform andaccompanying switching noise when data electrode high-voltage data isswitched, using a simple circuit configuration.

[0110] The present invention is described above in the form ofembodiments, and it will be understood that the present invention is notrestricted to the foregoing embodiments, and can be embodied in othervariations, within the technical scope of the present invention. Forexample, the plasma display panel to which the data driver circuit ofthe present invention is not restricted to an AC drive type, and canalternatively be a DC drive type plasma display panel. Furthermore, thedisplay is not restricted to a color plasma display panel, and canalternatively be a monochrome plasma display panel. It should also beunderstood that it is not required that the plasma display panel be asub-field drive type plasma display panel.

[0111] In the foregoing first embodiment, second embodiment, and thirdembodiment, because it is sufficient that the gate circuits L1, L2, L3,L4, and so on be capable of imparting a prescribed time differencebetween output signals from the even-numbered gates and the odd-numberedgates, it is possible to delay the output signals from the outputcontrol logic gate circuits at the odd-numbered gate circuits L1, L3,and so on, and also possible to omit the odd-numbered gate circuits L1,L3, and so on. In the third embodiment it is possible in the data leveldifference signal generating circuit/time difference generating circuit14, to set the threshold values not by the threshold value settingcircuit 23, but by supplying various threshold level signals from theoutside.

[0112] A data driver circuit according to the foregoing embodiments issuitable for implementation as an integrated circuit, and by providing aplurality of data driver circuits within a plasma display panel device,and controlling the time difference of data signal outputs at adjacentdata electrodes for each data driver circuit separately, it is possibleto perform control in small circuit units, thereby greatly improving theeffectiveness in reducing noise.

[0113] According to a data driver circuit of the present inventionconfigured as described in detail above, by dividing data electrodes towhich data signals are supplied from the data driver circuit intoeven-numbered and odd-numbered electrodes, detecting a condition inwhich the potentials on adjacent electrodes change to be the samepotential at the same time, and imparting a time difference between thedata signals output from odd-numbered data electrodes and the datasignals output from even-numbered data electrodes, it is possible toeasily achieve a charging/discharging load for the inter-electrodecapacitance, thereby suppressing a sudden change in the voltage waveformwhen the high-voltage data signals at data electrodes are switched andreducing the associated switching noise.

What is claimed is:
 1. A data driver circuit for a plasma display devicehaving a first data electrode and a second electrode that are disposedadjacently to each other, said data driver circuit comprising: a firstcircuit means for outputting first display data to said first dataelectrode; a second circuit means for outputting second display data tosaid second data electrode; and an output timing control means forcontrolling a timing of outputting said first display data from saidfirst circuit means to said first data electrode or a timing ofoutputting said second display data from said second circuit means tosaid second data electrode.
 2. A data driver circuit for a plasmadisplay device having a first data electrode and a second electrode thatare disposed adjacently to each other, said data driver circuitcomprising: a first latch circuit for latching first display data foroutputting to said first data electrode; a second latch circuit forlatching second display data for outputting to said second dataelectrode; a first latch signal for said first latch circuit; a secondlatch signal for said second latch circuit; and a latch timing controlmeans for controlling a latch timing of said first display data by saidfirst latch signal or a latch timing of said second display data by saidsecond latch signal; wherein said latch timing of said second latchcircuit is different from that of said first latch circuit.
 3. The datadriver circuit according to claim 2, wherein said data driver circuitfurther comprising: a time difference generating means for controllingsaid latch timing control means in accordance with said first displaydata and said second display data; wherein said time differencegenerating means generates a time difference between said latch timingof said first latch circuit and said latch timing of said second latchcircuit.
 4. A data driver circuit for a plasma display device having afirst data electrode and a second electrode that are disposed adjacentlyto each other, said data driver circuit comprising: a first circuitmeans for outputting first display data to said first data electrode ata first timing; a second circuit means for outputting second displaydata to said second data electrode at said first timing or a secondtiming that is different from said first timing; and an output timingcontrol means for selecting either said first timing or said secondtiming so as to control an output timing of said second circuit means.5. A data driver circuit for a plasma display device having a first dataelectrode and a second electrode that are disposed adjacently to eachother, said data driver circuit comprising: a first latch circuit forlatching first display data for outputting to said first data electrode;a second latch circuit for latching second display data for outputtingto said second data electrode; a latch signal for said second latchcircuit; and a latch timing control means for controlling a latch timingof said second display data by said latch signal; wherein said latchtiming of said second latch circuit is different from that of said firstlatch circuit.
 6. The data driver circuit according to claim 5, whereinsaid data driver circuit further comprising: a time differencegenerating means for controlling said latch timing control means inaccordance with said first display data and said second display data;wherein said time difference generating means generates a timedifference between said latch timing of said first latch circuit andsaid latch timing of said second latch circuit.
 7. A data driver circuitfor a plasma display device having a first data electrode and a secondelectrode that are disposed adjacently to each other, said data drivercircuit comprising: a first latch circuit for latching first displaydata for outputting to said first data electrode; a second latch circuitfor latching second display data for outputting to said second dataelectrode; a first latch signal for said first latch circuit; and asecond latch signal, a latch timing of which being different from thatof said first latch circuit, for said second latch circuit.
 8. A datadriver circuit for a plasma display device having a first data electrodeand a second electrode that are disposed adjacently to each other, saiddata driver circuit comprising: a first circuit means for outputtingfirst display data to said first data electrode; a second circuit meansfor outputting second display data to said second data electrode; and adelay means provided in said second circuit means so as to delay anoutput timing of said second display data with respect to that of saidfirst display data.